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[VHDL-FPGA-Verilog] 16Bit-Group-Ripple-Adder

Description: Verilog Testbench for 16Bit Group Ripple Adder
Platform: | Size: 29696 | Author: Raz | Hits:

[source in ebook] fpga

Description: 有关FPGA的好多资料的综合汇总，包括夏宇闻-Verilog经典教程，Verilog-testbench的写法，Altera+FPGA／CPLD设计高级篇，Altera+FPGA／CPLD设计基础篇等好几本书，超值-A comprehensive summary of a lot of information about FPGA, including Xia Wen-Verilog classic tutorial, Verilog-testbench writing, senior Altera+FPGA/CPLD/CPLD design, Altera+FPGA design based on articles such as several book value
Platform: | Size: 48264192 | Author: libao | Hits:

[VHDL-FPGA-Verilog] i2c_master

Description: verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)
Platform: | Size: 3072 | Author: Teray | Hits:

[VHDL-FPGA-Verilog] i2c_slave

Description: Verilog i2c slave rtl + testbench 仿真ok(Verilog i2c slave rtl + testbench)
Platform: | Size: 8192 | Author: Teray | Hits:

[VHDL-FPGA-Verilog] I2C_slaver_verison3.0

Description: I2C从机模块，包含testbench，平台是vivado,仿真测试通过。(I2C slave module, including testbench, the platform is vivado, simulation test passed.)
Platform: | Size: 2095104 | Author: wenxulyu | Hits:

[VHDL-FPGA-Verilog] New folder

Description: clock div testbench design and frquency division
Platform: | Size: 3072 | Author: Bharadwaj | Hits:

[VHDL-FPGA-Verilog] SEQ_DETECTOR

Description: 这是一个四位串行数据检测器，一共有三种模式可以选择：递增（检测连续四位递增序列），递减（检测连续四位递减序列）和不变（检测连续四位不变序列）。整个设计采用同步时钟，异步复位，用米利状态机，并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data), decrement mode (detecting four consistency decrement data) and steadiness mode (detecting four consistency same data). The whole design adopts synchronous clock, asynchronous reset, and uses Mealy state machine. The whole file concludes the simulation environment and testbench.)
Platform: | Size: 1855488 | Author: LLawliet | Hits:

[Other] anc dec

Description: encoder,decoder,testbench and run files
Platform: | Size: 27648 | Author: Gops | Hits:

[VHDL-FPGA-Verilog] uygulama1

Description: verilog hdl, haladder testbench
Platform: | Size: 1495040 | Author: mrv | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用Verilog实现FPGA的uart的串行通信功能，并附有testbench(The serial communication function of FPGA of UART is realized with Verilog, and Testbench is attached)
Platform: | Size: 308224 | Author: 怪了个乖 | Hits:

[VHDL-FPGA-Verilog] ADC_Data_Recv_Module

Description: 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated data The compressed package includes the Verilog code, the testbench code Matlab simulation code)
Platform: | Size: 512000 | Author: nokkk | Hits:

[VHDL-FPGA-Verilog] Clock_Synchronization_Module

Description: 数字接收机中频部分数字时钟的设计 包括matlab仿真 verilog代码、 testbench代码 以及word设计文档(Design of medium frequency digital clock in digital receiver Including Matlab simulation Verilog, testbench code, and design documents)
Platform: | Size: 245760 | Author: nokkk | Hits:

[VHDL-FPGA-Verilog] float_adder

Description: 实现可调维度的浮点数加法运算，内涵各个子模块和testbench(Able to achieve the float numbers adding operation.)
Platform: | Size: 82944 | Author: 聪明的Jerry | Hits:

[VHDL-FPGA-Verilog] frequency divider and testbench

Description: a frequency divider and test bench with simulation results
Platform: | Size: 493568 | Author: abitofhero | Hits:

[Crack Hack] aes-master

Description: Verilog写的AES加密解密代码，带testbench。(AES encryption code written by Verilog with testbench.)
Platform: | Size: 69632 | Author: 容止 | Hits:

[Other] electrical lock

Description: 一个用Verilog写的电子锁工程，带testbench。(An electronic lock project written in Verilog with testbench.)
Platform: | Size: 2627584 | Author: 容止 | Hits:

[VHDL-FPGA-Verilog] FP_adder

Description: 32 bit floating point adder with testbench
Platform: | Size: 11264 | Author: liki20 | Hits:

[VHDL-FPGA-Verilog] HDL_equation

Description: Verilog Program to implement the function f=x+yz and Testbench for all the possible inputs using For Loop
Platform: | Size: 5120 | Author: liki20 | Hits:

[VHDL-FPGA-Verilog] adder

Description: 实现了加法器功能，包含testbench(Implements the adder function)
Platform: | Size: 1024 | Author: 心向远方93 | Hits:

[Embeded-SCM Develop] spi slave程序

Description: spi slave的verilog程序，有测试平台testbench程序，实现fpga作为salve的功能(spi slave verilog program)
Platform: | Size: 5120 | Author: CARL_2018 | Hits:
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